1. Field of the Invention
The present invention relates to an analog circuit of, for example, a communication device and so on, and particularly relates to an analog-digital converter, a signal processor, and a receiving device.
2. Description of the Related Art
In a communication device including an analog-digital converter (hereinafter, called as an “A/D converter”, “ADC”), it is necessary to adjust an input signal amplitude to be enough larger than a minimum resolution of the ADC and smaller than a maximum input signal amplitude of the ADC. As a method to adjust the input signal amplitude, for example, a method to use a variable gain amplification circuit can be cited, but in the variable gain amplification circuit, a problem is known in which a direct current offset varies. In particular, when a gain is controlled with following to a variation of received signal intensity in a radio communication in which the intensity varies, the direct current offset of an output may vary in accordance with the variation of the gain. Generally, the direct-current offset is removed by a feedback control and so on, but there is a problem that communication quality may deteriorate until a transient response converges. To avoid this problem, a method is studied in which an input dynamic range of the ADC is enlarged and a variable range of the variable gain amplification circuit is reduced, or the variable gain amplification circuit in itself is omitted.
Meanwhile, a study for a delta-sigma type analog-digital converter (DSADC) is in progress, in which a continuous time filter enabling an omission of an anti-alias filter required for the ADC is used (refer to L. J. Breems and others, “A 1.8 mW CMOS ΣΔ Modulator with Integrated Mixer for A/D Conversion of IF Signals”, IEEE Journal of Solid-State Circuits, April, 2000, Vol. 35, No. 4, p. 468 to p.
475). In the document of L. J. Breems and others, an example is reported, in which a frequency conversion circuit down-converting an IF signal of 50 MHz and a DSADC operating with a clock of 13 MHz are connected directly.
However, when the frequency conversion circuit and the DSADC described in the above document are applied to a radio receiver such as a cellular phone, it is necessary to supply a high frequency signal with low impedance for the extent that it does not affect a circuit operation. Accordingly, a high-frequency buffer amplifier consuming a relatively large current is necessary. In addition, a DAC for feedback constituting the DSADC in itself is a switch, and therefore, a power consumption thereof is small. However, a direct-current voltage supply circuit having enough low output impedance is necessary so as not to generate a voltage variation by an ON/OFF operation of the switch of the DAC, to supply a reference voltage to the DAC. Namely, there has been a problem that an elimination of power consumption is difficult as a total because the power consumption with including peripheral circuits increases conversely in the frequency conversion circuit and the DSADC described in the above document.